1. Field of the Invention
This invention relates to a thin film transistor substrate applied to a display device, and more particularly to a thin film transistor substrate and a fabricating method thereof that are adaptive for simplifying a process.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a thin film transistor substrate and a color filter substrate opposed to each other, a liquid crystal injected between two substrates, and a spacer maintaining cell gap between the two substrates.
The thin film transistor substrate includes gate lines, data lines, thin film transistors formed as switching devices for each crossing between the gate lines and the data lines, pixel electrodes formed for each liquid crystal cell and connected to the thin film transistor, and alignment films formed thereon. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel signal fed to the data line to the pixel electrode in response to a scanning signal fed to the gate line.
The color filter substrate includes color filters formed for each liquid crystal cell, black matrices for dividing color filters and reflecting an external light, common electrodes for commonly applying reference voltages to the liquid crystal cells, and an alignment film formed thereon.
The liquid crystal display panel is completed by preparing the thin film array substrate and the color filter substrate individually to join them and then injecting a liquid crystal between them and sealing it.
In such a liquid crystal display device, the thin film transistor substrate has a complicated fabrication process that leads to a major rise in a manufacturing cost of the liquid crystal display panel because it involves a semiconductor process and needs a plurality of mask processes. In order to solve this, the thin film transistor substrate has been developed toward a reduction in the number of mask processes. This is because one mask process includes processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, there has been highlighted a four-mask process excluding one mask process from the existent five-round mask process that was a standard mask process of the thin film transistor.
FIG. 1 is a plan view illustrating a thin film transistor substrate using a four-mask process, and FIG. 2 is a section view of the thin film transistor substrate taken along the I-I′ line in FIG. 1.
In FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 42 in such a manner to cross each other while with having a gate insulating film 44 therebetween, a thin film transistor 6 provided at each crossing, and a pixel electrode 18 provided at a cell area having the crossing structure. Further, the thin film transistor substrate includes a storage capacitor 20 provided at an overlapped portion between the pixel electrode 18 and a previous gate line 2, a gate pad 26 connected to the gate line 2, and a data pad 34 connected to the data line 4.
The thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged into the pixel electrode 18 and kept in response to a scanning signal applied to the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18, and an active layer 14 overlapping with the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12.
The active layer 14 overlapping with the source electrode 10 and the drain electrode 12 and having a channel portion between the source electrode 10 and the drain electrode 12 also overlaps with the data line 4, a lower data pad electrode 36 and a storage electrode 22. On the active layer 14, an ohmic contact layer 48 for making an ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36 and the storage electrode 22 are further provided.
The pixel electrode 18 is connected, via a first contact hole 16 passing through a passivation film 50, to the drain electrode 12 of the thin film transistor 6. The pixel electrode 18 generates a potential difference with respect to a common electrode provided at an upper substrate (not shown) by the charged pixel signal. This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the upper substrate owing to a dielectric anisotropy and transmits a light input, via the pixel electrode 18, from a light source (not shown) toward the upper substrate.
The storage capacitor 20 includes a previous gate line 2, a upper storage electrode 22 overlapping the gate line 2 and having the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween, and a pixel electrode 18 overlapping the upper storage electrode 22 and having the passivation film 50 therebetween and connected via a second contact hole 24 passing through the passivation film 50. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 18 to be stably maintained until a next pixel voltage is charged.
The gate line 2 is connected, via the gate pad 26, to a gate driver (not shown). The gate pad 26 consists of a lower gate pad electrode 28 extended from the gate line 2, and an upper gate pad electrode 32 connected, via a third contact hole 30 passing through the gate insulating film 44 and the passivation film 50, to the lower gate pad electrode 28.
The data line 4 is connected, via the data pad 34, to the data driver (not shown). The data pad 34 includes a lower data pad electrode 36 extended from the data line 4, and an upper data pad electrode 40 connected, via a fourth contact hole 38 passing through the passivation film 50, to the lower data pad electrode 36.
Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure using the four-mask process will be described in detail with reference to FIG. 3A to FIG. 3D.
In FIG. 3A, a gate pattern including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28 is provided on the lower substrate 42 by the first mask process.
More specifically, a gate metal layer is formed on the lower substrate 42 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by a photolithography and etching process using a first mask to thereby form a gate pattern including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28. The gate metal layer may have a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc.
In FIG. 3B, the gate insulating film 44 is formed on the lower substrate 42 provided with the gate pattern. Further, a semiconductor pattern including the active layer 14 and the ohmic contact layer 48 and source/drain pattern including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36 and the storage electrode 22 are sequentially provided on the gate insulating film 44 by the second mask process.
More specifically, the gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate 42 provided with the gate pattern by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 44 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal may be selected from molybdenum (Mo) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by the photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to thereby provide the source/drain pattern including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height is removed from the channel portion by a ashing process and thereafter the source/drain pattern and the ohmic contact layer 48 of the channel portion are etched by the dry etching process. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12.
Then, the photo-resist pattern left on the source/drain metal pattern group is removed by a stripping process.
In FIG. 3C, the passivation film 50 including the first to fourth contact holes 16, 24, 30 and 38 are formed on the gate insulating film 44 provided with the source/drain pattern.
More specifically, the passivation film 50 is formed entirely on the gate insulating film 44 provided with the source/drain pattern by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). Then, the passivation film 50 is patterned by the photolithography and etching process using a third mask to thereby define the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed in such a manner to pass through the passivation film 50 and expose the drain electrode 12, whereas the second contact hole 24 is formed in such a manner as to pass through the passivation film 50 and expose the upper storage electrode 22. The third contact hole 30 is formed in such a manner as to pass through the passivation film 50 and the gate insulating film 44 and expose the lower gate pad electrode 28. The fourth contact hole 38 is formed in such a manner as to pass through the passivation film 50 and expose the upper data pad electrode 36.
The passivation film 50 is formed of an inorganic insulating material identical to the gate insulating film 44, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
In FIG. 3D, a transparent conductive pattern including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40 is provided on the passivation film 50 by the fourth mask process.
A transparent conductive layer is formed on the passivation film 50 by a deposition technique such as sputtering, etc. Then, the transparent conductive layer is patterned by photolithography and an etching process using a fourth mask to thereby provide the transparent conductive pattern including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the upper storage electrode 22 overlapping with a previous gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. Herein, the transparent conductive layer is formed of indium-tin-oxide (ITO), etc.
As described above, the related art thin film transistor substrate and the fabricating method uses a four-mask process, thereby reducing the number of processes and hence reducing manufacturing costs in proportion to the reduction in the number of processes.
However, in the related art thin film transistor substrate, the upper and lower electrodes of the storage capacitor 20 are formed of an opaque source/drain metal and an opaque gate metal, respectively. Thus, the problem arises in that, when an overlapping area between the upper storage electrode 22 and the gate line 2 is enlarged so as to increase a capacitance of the storage capacitor 20, an aperture ratio of the pixel electrode 18 is reduced.